The present invention relates to a method of manufacturing a semiconductor integrated circuit device (hereinbelow, termed "Bi-MOS IC") in which bipolar transistors and metal-insulator-semiconductor field effect transistors, e.g., metal-oxide-semiconductor field effect transistors, hereinbelow termed "MOS FETs", are formed within a single semiconductor body.
There have heretofore been developed various processes by which bipolar transistors and n-channel MOS FETs (N-MOS FETs) or complementary MOS FETs (C-MOS FETs) are caused to coexist within a single semiconductor body. An example of conventional processes is as described below:
1 An n.sup.+ -type buried layer is formed in a part of the major surface of a p-type silicon (Si) substrate. Further, an n-type Si layer is epitaxially grown on the p-type Si substrate.
2 Boron (B) is diffused from parts of the surface of the n-type epitaxial layer so as to form p-type diffused layers for isolation reaching the p-type substrate, thereby to form several electrically-isolated island regions within the n-type Si layer.
3 In another part of the n-type epitaxial layer, a deep p-type region (usually called "p-type well") is formed by similar boron diffusion from the surface of the epitaxial layer.
4 An n-channel MOS FET is formed in the p-type well region. On the other hand, a p-channel MOS FET and a bipolar transistor are formed in the other island regions within the n-type Si layer.
The above process is disclosed in the official gazette of Japanese Laid-Open Patent Application No. 54-131887.
Such process is directed toward a Bi-MOS IC in which the thickness of the epitaxial n-type silicon layer is approximately 10 .mu.m or greater (the depth of an emitter is approximately 5 .mu.m). Recently, ICs have been refined in order to enhance the operating speeds of elements or to reduce the chip area. In this regard, when the thickness of an epitaxial Si layer becomes as small as below 5 .mu.m, the foregoing process brings about the problem that the base-collector breakdown voltage of the bipolar n-p-n transistor lowers.
More specifically, the p-type well for forming the n-channel MOS FET must be rendered deep to some extent (approximately as deep as the epitaxial layer) in order to ensure the source-drain breakdown voltage of the n-channel MOS FET to be formed in the major surface of the well. On the other hand, since the surface density of the p-type well determines the V.sub.th (threshold voltage) of the MOS FET, the diffusion of an impurity at a high density is undesirable. In forming the p-type well, therefore, the diffusion treatment needs to be performed at a low density (C.sub.s .apprxeq.1.times.10.sup.16 cm.sup.-3) as well as a high temperature (1200.degree. C.) and for a long time of 4-6 hours. At the heat treatment, an n-type impurity (such as Sb and P) diffuses from the n.sup.+ -type buried layer, located just under the base layer of the bipolar transistor, upwardly into the epitaxial layer as high as about 3.5 .mu.m and reaches the vicinity of the base layer of the n-p-n transistor. In consequence, the collector-base breakdown voltage lowers.
Therefore, when the upward extension of the n.sup.+ -type buried layer is taken into account, the thickness of the epitaxial layer is limited to 7 .mu.m as the minimum value. It has been difficult to refine the Bi-MOS IC by forming it at a smaller thickness and to enhance the operating speed of the bipolar transistor.
A second technique, different from the present invention but similar thereto, is disclosed in the official gazette of Japanese Laid-Open Patent Application No. 57-75453. The disclosed process, however, must introduce impurities from the surface of a semiconductor body by separate steps in order to form an isolation region and a p-type well region and has the disadvantage of a larger number of steps.